1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a phase-change random access memory device and a method for manufacturing the same, capable of reducing an amount of current required for phase-changing a phase-change layer by reducing a contact area between a bottom electrode and the phase-change layer.
2. Description of the Prior Art
Semiconductor memory devices are mainly classified into RAM (random access memory) devices, such as DRAM (dynamic random access memory) devices and SRAM (static random access memory) devices, and ROM (read only memory) devices. The RAM devices have volatile characteristics so that data stored therein are automatically erased as time goes by. In addition, the RAM devices may allow data to be inputted thereto or outputted therefrom at a relative high speed. The ROM (read only memory) devices can permanently store data while allowing data to be inputted thereto or outputted therefrom at a relative low speed. Such memory devices may represent logic “0” or logic “1” depending on charges stored therein.
Herein, the DRAM device, which is a volatile memory device, is unable to retain data unless a refresh voltage is periodically applied thereto, so it requires higher charge storage capacity. For this reason, various attempts have been carried out in order to enlarge a surface area of a capacitor electrode. However, if the surface area of the capacitor electrode becomes enlarged, there is a difficulty to increase an integration degree of the DRAM device.
In contrast, a non-volatile memory device has a greater amount of charge storage capacity. Recently, demands for flash memory devices, such as EEPROM (electrically erasable and programmable ROM) devices, allowing data to be electrically inputted/outputted have been being substantially increased.
Such a flash memory cell generally has a vertical-stack type gate structure including a floating gate formed on a silicon substrate. Typically, A multi-gate structure includes at least one tunnel oxide layer or dielectric layer, and a control gate formed at an upper portion or a peripheral portion of the floating gate. Writing or erasing of data in the flash memory cell can be achieved by allowing charges to pass through the tunnel oxide layer. At this time, an operation voltage must be higher than a supply voltage. For this reason, the flash memory devices must be equipped with booster circuits so as to generate voltages required for writing or erasing the data.
Thus, there have been various attempts to develop new memory devices having non-volatile and random access characteristics capable of increasing the integration degree thereof with a more simple structure. One example of such new memory devices is a phase-change random access memory (PRAM) device.
The phase-change random access memory device employs a chalcogenide layer as a phase-change layer. The chalcogenide layer is a compound layer including Ge, Sb and Te (hereinafter, referred to as a “GST layer”). The GST layer is electrically switched between an amorphous state and a crystalline state according to current applied thereto, that is, Joule heat applied thereto.
FIG. 1 is a graph for explaining a method of programming or erasing data in a phase-change random access memory device, in which a transverse axis represents a time and a longitudinal axis represents a temperature of a phase-change layer.
As shown in FIG. 1, if the phase-change layer is rapidly quenched after the phase-change layer has been heated at a first predetermined temperature higher than a melting temperature (Tm) for a first period of time (t1: first operation period), the phase-change layer is changed into an amorphous state (see, curve ‘A’). In contrast, if the phase-change layer is quenched after the phase-change layer has been heated at a second predetermined temperature lower than the melting temperature (Tm) and higher than a crystallization temperature (Tc) for a second predetermined period of time (t2: second operation period) longer than the first operation period t1, the phase-change layer is changed into a crystalline state (see, curve ‘B’).
Herein, resistivity of the phase-change layer in the amorphous state is higher than that of the phase-change layer in the crystalline state. Therefore, it is possible to determine whether information stored in the phase-change random access memory cell is logic “1” or logic “0” by detecting current applied to the phase-change layer in a read mode.
As mentioned above, Joule heat is necessary in order to phase-change the phase-change layer. In a conventional phase-change random access memory device, if high density current is applied to a contact surface of the phase-change layer, the crystalline state of the contact surface of the phase-change layer may be changed. At this time, it is noted that current density required for phase-changing the phase-change layer becomes lowered as the contact surface of the phase-change layer becomes reduced.
FIG. 2 is a sectional view for explaining a conventional phase-change random access memory device.
As shown in FIG. 2, the conventional phase-change random access memory device includes a semiconductor substrate 10 formed with a bottom electrode 11, a first insulation layer 12 formed on the bottom electrode 11 and having a first contact hole 13 for exposing a predetermined portion of the bottom electrode 11, a bottom electrode contact 14 for filling the first contact hole 13, a second insulation layer 15 formed on the first insulation layer 12 including the bottom electrode contact 14 and having a second contact hole 16 for exposing the bottom electrode contact 14, a phase-change layer 17 for filling the second contact hole 16, and a top electrode 18 formed on the second insulation layer 15 including the phase-change layer 17.
In such a conventional phase-change random access memory device, if current is applied between the bottom electrode 11 and the top electrode 18, the crystalline state of the phase-change layer 17 is changed at a contact surface 19 according to current intensity (that is, heat) applied to the contact surface 19 formed between the bottom electrode contact 14 and the phase-change layer 17. At this time, heat required for phase-changing the phase-change layer 17 may directly relate to the contact surface 19 formed between the bottom electrode contact 14 and the phase-change layer 17. Accordingly, it is necessary to minimize the size of the contact surface 19, if possible.
However, in the above conventional phase-change random access memory device, the bottom electrode 11 is connected to the phase-change layer 17 through the bottom electrode contact 14. Accordingly, the size of the contact surface between the bottom electrode contact 14 and the phase-change layer 17 is directly subject to a limitation of a photo process for the contact hole, so there is a difficulty to reduce the size of the contact surface. For this reason, an amount of current required for phase-changing the phase-change layer may increase.